Renesas Electronics · Plano, TX

Principal Analog Sustaining Engineer at Renesas Electronics — Plano, TX

Full-timePlano, TXPosted 2026-07-23Apply on SmartRecruiters

Full job description

A key technical engineer tasked with investigating and resolving field failures and customer-reported issues on top-tier automotive PMIC products. Operating at the intersection of silicon behavior, system-level debugging, and customer interaction, lead root cause analysis from initial RMA intake to final resolution and knowledge sharing. Collaborate closely with customer applications teams, FA labs, and cross-functional engineering groups to deliver reliable, data-driven solutions for our customers.

Principal Accountabilities

  • RMA Onboarding & Reproduction Setup: Review RMA documentation and debug history to understand failure symptoms; set up simulation and/or hardware debug environments to reproduce reported issues.
  • Waveform & Silicon Analysis: Collect and analyze waveforms, run analog simulations, and review RTL/netlist to identify potential failure mechanisms and silicon behavior anomalies.
  • Collaborative Debugging: Work closely with customer applications teams to align on debugging focus, share regular status and progress updates, and drive structured investigation plans.
  • Advanced Failure Analysis: Initiate further analysis where required (e.g., FA lab), interpret results, and plan next actions to converge on root cause.
  • Customer-Facing Technical Documentation: Create high-quality materials for customers including presentations, 8D reports, and any other relevant technical documents throughout the investigation lifecycle.
  • Fix & Workaround Proposals: Propose silicon fixes or system-level workarounds, outline validation strategies, and review feasibility with customer applications teams and relevant internal departments.
  • Root Cause Analysis Reports: Deliver comprehensive debug reports covering root cause analysis (RCA), fix proposals, and supporting data in a clear and structured format for both internal and external stakeholders.
  • Technical Handoff & Closure: Conduct technical handoff meetings to ensure smooth knowledge transfer and formal case closure with all relevant teams.
  • Cross-functional Collaboration: Engage with design, applications, test, and quality engineering teams to share learnings, drive design improvements, and contribute to sustaining quality initiatives.
  • Ensure impactful dissemination of knowledge across Renesas design teams for lessons learned.
  • Demonstrate risk astuteness, proactively implementing solutions with minimal input from the Manager
  • Recognition for technical expertise in analog design across PMIC organization, demonstrated through proactive use of forums eg lunch and learns / skills training
  • Demonstrate elements of Renesas values in all aspects of work
  • Demonstrate continuous improvement of technical and non-technical skills, measured through manager review.
  • Typically 12-15+ years' experience in IC design, with a strong focus on debug, failure analysis, or sustaining engineering
  • Strong analytical mindset with the ability to drive structured, data-driven root cause investigations independently and collaboratively
  • Demonstrated experience diagnosing complex silicon or system-level failures across mixed-signal PMIC environments
  • Solid understanding of analog and digital circuit behavior, waveform analysis, and how design implementation manifests on silicon.
  • Hands-on experience with industry-standard EDA and debug tools (e.g., Synopsys, Cadence, oscilloscopes, logic analyzers, simulation environments)
  • Strong attention to detail and accuracy, with the ability to produce clear, concise technical reports and customer-facing documentation
  • Excellent written and verbal cross-functional communication skills, including experience presenting technical findings to customers
  • Structured problem-solving approach – open to new perspectives and able to build consensus across engineering and customer teams
  • Experience with FA lab processes, failure analysis techniques (e.g. SEM, FIB, emission microscopy), and interpretation of physical failure analysis results
  • Knowledge of Verilog, Verilog-AMS or scripting languages used to support debug automation or simulation
  • Familiarity with 8D problem-solving methodology, structured debug reports, and customer quality processes

Education

  • BSEE or MSEE (Bachelor's or Master's in Electrical Engineering)