Senior Staff CAD Engineer, Multi-die 3DIC & Power — Santa Clara, CA

About Marvell

Your Team, Your Impact

As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation Multi-die and Power Methodology, plus CAD flow automation and tool support. You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's methodology and workflow.

What You Can Expect

• Develop and maintain next-gen CAD Flows & Methodologies for Multi-die and Power to address the needs of Marvell's various Business Units.
• Contribute to the deployment, support, and regressions of these flows.
• Collaborate with Infrastructure teams to ensure optimal flow integration within the larger CAD framework.
• Explore opportunities for agentic AI/ML tools and projects.
• Drive weekly engagement with external partners and internal customers to track product requirements and EDA tool development.
• Display strong analytical and problem-solving skills.
• Participate in industry events and follow industry trends.
• Demonstrate a constant interest in new ideas and new learning, potentially beyond the topics described above.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of

experience

• 3+ years of hands-on experience in physical design and flow development in an ASIC rtl-to-gds environment
• Strong proficiency in TCL and python scripting for CAD flow development
• Comfortable working in an agile environment with constant learning and innovation
• Strong verbal and written communication skills
• Experience with multi-die topics
• 2.5D/3D/3.5D die-stacking, floorplanning, SOIC hybrid bonding
• Inter-die extraction, multi-die analysis (IR, STA, thermal)
• Advanced packaging technologies: CoWoS, EMIB, PIVR, COUPE
• Interposer routing for silicon & fanout, SI/PI analysis

•

• Experience with power analysis topics
• RTL power estimation & optimization, clock-gating efficiency
• ASIC block power, glitch power, UPF
• Experience with industry tools
• 3DIC Compiler, Integrity 3DIC, Fusion Compiler, Innovus
• PrimePower, PP-RTL, Empower, Joules, PowerArtist

Expected Base Pay Range (USD)

127,630 - 191,200, $ per annum

Interview Integrity

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