Senior Staff Engineer, Digital IC Design at 31 MSI - (Marvell Semiconductor Inc.) US — Santa Clara, CA

About Marvell

Your Team, Your Impact

The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high-performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores

What You Can Expect

• Work with SOC Integration team to integrate internal and external IP blocks at the chip level.
• Take ownership of a portion of an SOC design and drive it from initial stages to completion
• Collaborate on floorplan
• Responsibility for interconnection of IP blocks
• Static checks
• Assist with subsystem and chip level verification efforts
• Drive to timing closure
• Collaborate with cross-disciplinary team including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements to tape-out a high quality, zero-defect product.
• Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip level.
• Lead design effort for internally developed processor IP blocks to meet specific architectural needs.
• Work closely with verification and implementation teams to meet product requirements.
• Deliver micro-architectural specifications for these designs.
• Utilize and participate in the development of automation tools to accelerate the pace of development.
• Leverage next-generation AI tools to enhance existing workflows.

What We're Looking For

• Bachelor’s degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of related professional experience. Or
• Master’s degree and/or PhD in Computer Engineering, Electrical Engineering or related fields with 3+ years of experience.
• Proven experience in taping out complex SoCs and post silicon debug
• Strong RTL design skills in SystemVerilog
• Hands-on experience with SoC integration and debug, along with clock/reset design, CDC, and timing constraints.
• Understanding of how front-end RTL decisions impact physical implementation and verification.
• Familiarity with industry standard ARM protocols (Ex: APB, AHB, AXI, CHI) and SoC interconnect (NOC) architectures.
• Excellent communication skills and ability to participate in problem-solving and quality improvement activities.
• Demonstrates good analytical and problem-solving skills.
• Experience with scripting languages, e.g., Python or Tcl

Expected Base Pay Range (USD)

134,390 - 201,300, $ per annum

Interview Integrity

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