Senior Staff Engineer, Digital IC Design at 31 MSI - (Marvell Semiconductor Inc.) US — Morrisville, NC

About Marvell

Your Team, Your Impact

The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores

What You Can Expect

• Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
• Work closely with system and chip architects to design industrial quality implementations.
• Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
• Produce comprehensive block uArchitecture and register Specs.
• Schedule detailed reviews with cross-functional teams
• Evaluate and participate in improving design and verification methodologies.

What We're Looking For

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10+ years of related professional experience. Or Master’s/PhD in Computer Science, Electrical Engineering or related fields with 3-5+ years of experience.

To be successful in this role you will need the following skills:

• Strong background in SystemVerilog RTL coding techniques.
• Experience in high speed, multiple clock domain designs
• Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
• Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors
• RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
• Experience in implementation/timing closure for high speed design.
• Ability to create SVA assertions and apply formal verification concepts and tools
• Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers
• Excellent verbal and written communication
• Discipline and rigor in documentation
• Ability to work efficiently and influentially with team members across multiple sites
• Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Expected Base Pay Range (USD)

135,900 - 201,130, $ per annum

Interview Integrity

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